Skip to content

WFI: Reacquire control of the core in the debugger after it executes a WFI instruction #43

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
eyck merged 1 commit into from
Mar 7, 2026
Merged

WFI: Reacquire control of the core in the debugger after it executes a WFI instruction #43

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ if(NOT TARGET dbt-rise-core)
FetchContent_Declare(
dbt_rise_core_git
GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
GIT_TAG 8f181e19e14e3fe5cfba340b47795c7b48b7844a
GIT_TAG 5d1ab03db17819fc113d3c4182cf0cee666085f2
GIT_SHALLOW OFF
UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
)
Expand Down
6 changes: 6 additions & 0 deletions src/iss/debugger/riscv_target_adapter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,8 @@ template <typename ARCH> class riscv_target_adapter : public target_adapter_base
avail buf is 1 */
status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;

status trigger_debugger_stop_event() override;

/* Write all registers. buf is 4-byte aligned and it is in target
byte order */
status write_registers(const std::vector<uint8_t>& data) override;
Expand Down Expand Up @@ -183,6 +185,10 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
return Ok;
}

template <typename ARCH> status riscv_target_adapter<ARCH>::trigger_debugger_stop_event() {
core->cancel_wait();
return Ok;
}
template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
CPPLOG(TRACE) << "reading target registers";
data.clear();
Expand Down
15 changes: 14 additions & 1 deletion src/sysc/core2sc_adapter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -255,13 +255,24 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
void wait_until(uint64_t flags) {
SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
PLAT::wait_until(flags);
wfi_inst.store(true, std::memory_order_relaxed);
std::function<void(void)> f = [this]() {
while((this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
sc_core::wait(this->wfi_evt);
sc_core::wait(this->wfi_evt | this->debugger_stop_evt);
bool is_debugger_stop_evt = this->debugger_stop_evt.triggered();
if(is_debugger_stop_evt) break;
}
SCCINFO(this->owner->hier_name()) << "Got WFI event";
};
owner->exec_on_sysc(f);
wfi_inst.store(false, std::memory_order_relaxed);
}

void cancel_wait() {
if(wfi_inst.load(std::memory_order_relaxed) == true) {
SCCDEBUG(owner->hier_name()) << "Trigger debugger stop event";
this->debugger_stop_evt.notify(sc_core::SC_ZERO_TIME);
}
}

private:
Expand Down Expand Up @@ -344,8 +355,10 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
sysc::riscv::core_complex_if* const owner{nullptr};
util::LoggerDelegate log_delegate;
sc_core::sc_event wfi_evt;
sc_core::sc_event debugger_stop_evt;
unsigned to_host_wr_cnt = 0;
bool first{true};
std::atomic<bool> wfi_inst{false};
mutex_t sync_mtx;
};
} // namespace sysc
Expand Down